1. Technical Field
The embodiments described herein relate to an internal voltage generating circuit, and more particularly, to an internal voltage generating circuit using a charge pump.
2. Related Art
Conventional semiconductor memory apparatuses are supplied with an external power supply voltage VDD and a ground voltage VSS and generate an internal voltage required for internal operations.
The following voltages are used for internal operations of the semiconductor memory apparatus: a core voltage Vcore that is applied to a memory core region; a high voltage Vpp used to drive word lines and for overdriving; and a substrate bias voltage Vbb that is supplied as a bulk voltage of a semiconductor substrate.
In particular, in recent years, in order to improve drivability of a part of a circuit, a negative voltage having an absolute value that is equal to more than that of the substrate bias voltage Vbb has been used. For example, a low voltage VNDS is applied to a source of an NMOS transistor sense in a sense amplifier circuit. In this way, it is possible to improve a driving speed during the under-driving of a sense amplifier circuit.
Since the level of the low voltage VNDS is lower than that of the ground voltage VSS, a charge pump is provided to supply and pump charges.
FIG. 1 is a block diagram illustrating a conventional internal voltage generating circuit for generating the low voltage VNDS. Referring to FIG. 1, the internal voltage generating circuit includes a voltage detector 10, an oscillator 20, and a charge pump 30.
The voltage detector 10 detects the level of the low voltage VNDS and provides an oscillation control signal OSC_EN.
The oscillator 20 provides a pumping period signal VNOSC having a predetermined period in response to the result detected by the voltage detector 10. The oscillator 20 may be a ring oscillator composed of an inverter chain.
The charge pump 30 generates a desired low voltage VNDS in response to a pumping period signal VNOSC, which is an oscillation signal output from the oscillator 20. That is, the charge pump 30 is configured to pump charges according to the pumping period signal VNOSC until a predetermined voltage is obtained, to generate the low voltage VNDS. Meanwhile, in order to prevent the level of the low voltage VNDS from being excessively lowered the output low voltage VNDS is fed back to the voltage detector 10. When the low voltage VNDS that is fed back is excessively low, the voltage detector 10 provides a inactivated oscillation control signal OSC_EN to inactivate the oscillator 20. Then, the charge pump 30 is also inactivated.
However, in a low-power semiconductor memory apparatus, in a low external voltage (VDD) range, the speed of the pumping period signal of the internal voltage generating circuit decreases, which results in a low charge pumping performance of a charge pump.